Intel to Create RISC-V Development Platform with SiFive P550 Cores on 7nm in 2022

intel-to-create-risc-v-development-platform-with-sifive-p550-cores-on-7nm-in-2022

As part of SiFive’s announcements today, along with enabling SiFive IP on Intel’s Foundry Service offerings, Intel will be creating its own RISC-V development platform using its 7nm process technology. This platform, called Horse Creek, will feature several of SiFive’s new Performance P550 cores also being announced today, and will be paired with Intel’s DDR and PCIe IP technology.

On first reading into the press release, it isn’t 100% clear that Intel’s commentary discusses a platform with P550 as a host or as an add-in device: to quote Intel, ‘We are pleased to be a lead development partner with SiFive to showcase to mutual customers the impressive performance of their P550 on our 7nm Horse Creek platform’. Intel historically typically keeps its Creek family names, such as Boulder Creek, Cherry Creek, or Timber Creek, for socketed platforms – not for all-in-one embedded development platforms. Not only that, the wording makes it sound like we should consider a RISC-V core as an assistant core managing another part of a system.

However it would appear that Intel intends to make this a fully-featured development system, along similar lines to SiFive’s own HiFive Unmatched platform launched early this year. What makes this special is that Intel is committing to developing the SoC on its own 7nm process node, which provides a ‘simpler’ vehicle for Intel to test and ramp up its 7nm technology. This can be coupled with increasing interest in RISC-V development, and deploying a platform though Intel’s supply chain and distribution might have a far reach to put these in the hands of upcoming developers.

The new SiFive Performance P550 core at the heart of Horse Creek is SiFive’s highest performance processor to date, with the company quoting a SPEC2006int of 8.65 per GHz. It is a Linux-capable core, with full support for the RISC-V vector extension v1.0rc. It has a 13-stage triple-issue out-of-order microarchitecture with a private 32KB+32KB L1 cache and a private L2 cache (per core) The design supports four cores in a single cluster that can be paired up to 4 MB of shared L3.

The time scale for this platform coming to market is quite interesting. Despite Intel recently committed to bringing its 7nm to market in 2023 with the compute tile for its Meteor Lake processor as its first 7nm product, we’re being told that Horse Creek silicon will be ready in 2022, which would make Horse Creek its first 7nm product. For what it is worth, it’s unlikely that the Intel RISC-V solution is tile-based, but it might be easy enough to bring a small RISC-V chip development platform to market around then. The chip is likely to be small, so that might work in favor of its costs as well. A question does remain as to whether Intel’s involvement here is purely in the hardware, or whether there will be an Intel-based software stack to go along with it.

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